There is an increasing demand for smaller semiconductor devices with increased memory, computational power, and speed. However, continuous scaling down dimensions of semiconductor devices increases density, and the conventional fabrication techniques involve contacting a portion of a gate electrode over an isolation region, which wastes layout space and adversely affects density. One of the problems with tight dimensional requirements of the semiconductor device is the parasitic capacitance during pillar for gate (PC) and lower S/D contact containing trench silicide (TS) reduction. Another challenge is to improve the design and method of forming contacts directly over the functional portion of a gate to improve device density, e.g., around 10% area scaling is achievable with COAG.
A need, therefore, exists for scaled-down devices with an oxide spacer in a COAG for efficient enabling methodology.